? semiconductor components industries, llc, 2008 august, 2008 ? rev. 4 1 publication order number: ADP3110A/d ADP3110A dual bootstrapped, 12 v mosfet driver with output disable the ADP3110A is a single phase 12 v mosfet gate drivers optimized to drive the gates of both high ? side and low ? side power mosfets in a synchronous buck converter. the high ? side and low ? side driver is capable of driving a 3000 pf load with a 25 ns propagation delay and a 30 ns transition time. with a wide operating voltage range, high or low side mosfet gate drive voltage can be optimized for the best efficiency. internal adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both mosfets. the floating top driver design can accommodate vbst voltages as high as 35 v, with transient voltages as high as 40 v. both gate outputs can be driven low by applying a low logic level to the output disable (od ) pin. an undervoltage lockout function ensures that both driver outputs are low when the supply voltage is low, and a thermal shutdown function provides the ic with overtemperature protection. features ? all ? in ? one synchronous buck driver ? bootstrapped high ? side drive ? one pwm signal generates both drives ? anticross conduction protection circuitry ? od for disabling the driver outputs meets cpu vr requirement when used with patented flexmode controller ? these are pb ? free devices applications ? multiphase desktop cpu supplies ? single ? supply synchronous buck converters device package shipping ? ordering information so ? 8 (pb ? free) 98 units / rail ADP3110Akrz a = assembly location l = wafer lot y = year w = work week = pb ? free package marking diagrams pin connections so ? 8 d suffix case 751 1 8 drvl v cc 18 pgnd od swn in drvh bst http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 3110a alyw 1 8 dfn8 mn suffix case 506bj drvl v cc pgnd od swn in drvh bst (top view) 18 so ? 8 (pb ? free) 2500 tape & reel ADP3110Akrz ? rl dfn8 (pb ? free) 5000 tape & reel ADP3110Akcpz ? rl 1 l3e alyw 1 8
ADP3110A http://onsemi.com 2 figure 1. block diagram 8 1 4 7 5 6 2 3 v cc drvh bst swn drvl pgnd od in tsd uvlo v cc monitor falling edge delay monitor falling edge delay non ? overlap timers min drvl off timer start stop pin description so ? 8 dfn8 symbol description 1 1 bst upper mosfet floating bootstrap supply. a capacitor connected between bst and sw pins holds this bootstrap voltage for the high ? side mosfet as it is switched. the recommended capacitor value is between 100 nf and 1.0 f. an external diode is required with the ADP3110A. 2 2 in logic ? level input. this pin has primary control of the drive outputs. 3 3 od output disable. when low, normal operation is disabled forcing drvh and drvl low. 4 4 v cc input supply. a 1.0 f ceramic capacitor should be connected from this pin to pgnd. 5 5 drvl output drive for the lower mosfet. 6 6 pgnd power ground. should be closely connected to the source of the lower mosfet. 7 7 swn switch node. connect to the source of the upper mosfet. 8 8 drvh output drive for the upper mosfet.
ADP3110A http://onsemi.com 3 maximum ratings rating value unit operating ambient temperature, t a 0 to 85 c operating junction temperature, t j (note 1) 0 to 150 c package thermal resistance: so ? 8 junction ? to ? case, r jc junction ? to ? ambient, r ja (2 ? layer board) package thermal resistance: dfn8 (note 2) junction ? to ? case, r jc (from die to exposed pad) junction ? to ? ambient, r ja 45 123 7.5 55 c/w c/w c/w c/w storage temperature range, t s ? 65 to 150 c lead temperature soldering (10 sec): reflow (smd styles only) pb ? free (note 3) 260 peak c jedec moisture sensitivity level so ? 8 (260 peak profile) 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. internally limited by thermal shutdown, 150 c min. 2. 2 layer board, 1 in 2 cu, 1 oz thickness. 3. 60 ? 180 seconds minimum above 237 c. note: this device is esd sensitive. use standard esd precautions when handling. maximum ratings pin symbol pin name v max v min v cc main supply voltage input 15 v ? 0.3 v pgnd ground 0 v 0 v bst bootstrap supply voltage input 35 v wrt/pgnd 40 v < 50 ns wrt/pgnd 15 v wrt/sw ? 0.3 v wrt/sw sw switching node (bootstrap supply return) 35 v 40 v < 50 ns ? 5.0 v ? 10 v < 200 ns drvh high ? side driver output bst + 0.3 v ? 0.3 v wrt/sw ? 2.0 v < 200 ns wrt/sw drvl low ? side driver output v cc + 0.3 v ? 0.3 v dc ? 5.0 v < 200 ns in drvh and drvl control input 6.5 v ? 0.3 v od output disable 6.5 v ? 0.3 v note: all voltages are with respect to pgnd except where noted.
ADP3110A http://onsemi.com 4 electrical characteristics (note 4) (v cc = 12 v, t a = 0 c to +85 c, t j = 0 c to +125 c unless otherwise noted.) characteristic symbol condition min typ max unit supply supply voltage range v cc ? 4.6 ? 13.2 v supply current i sys bst = 12 v, in = 0 v ? 0.7 5.0 ma od input input voltage high v od _hi ? 2.0 ? ? v input voltage low v od _lo ? ? ? 0.8 v hysteresis ? ? 400 ? mv input current no internal pullup or pulldown resistors ? 1.0 ? +1.0 a pwm input input voltage high v pwm_hi ? 2.0 ? ? v input voltage low v pwm_lo ? ? ? 0.8 v hysteresis ? ? ? 400 ? mv input current ? no internal pullup or pulldown resistors ? 1.0 ? +1.0 a high ? side driver output resistance, sourcing current ? bst ? sw = 12 v ? 2.2 3.4 output resistance, sinking current ? bst ? sw = 12 v ? 1.0 1.8 output resistance, unbiased ? bst ? sw = 0 v ? 15 ? k transition times t rdrvh t fdrvh bst ? sw = 12 v, c load = 3.0 nf (see figure 3) ? 20 11 55 45 ns propagation delay times (note 5) t pdhdrvh t pdldrvh t pdlod t pdhod bst ? sw = 12 v, c load = 3.0 nf bst ? sw = 12 v, c load = 3.0 nf (see figure 3) (see figure 2) (see figure 2) 32 45 25 20 25 70 35 35 55 ns sw pulldown resitance ? sw to pgnd ? 15 ? k low ? side driver output resistance, sourcing current ? ? 1.8 3.4 output resistance, sinking current ? ? 1.0 1.8 output resistance, unbiased ? v cc = pgnd ? 15 ? k transition times t rdrvl t fdrvl c load = 3.0 nf, (see figure 3) ? 16 11 50 30 ns propagation delay times (note 5) t pdhdrvl t pdldrvl t pdlod t pdhod c load = 3.0 nf, (see figure 3) (note 6, t pdhdrvl only) (see figure 2) (see figure 2) ? 12 15 20 20 35 40 35 35 ns timeout delay ? drvh ? sw = 0 ? 85 ? ns undervoltage lockout uvlo startup ? ? 3.9 4.3 4.5 v uvlo shutdown ? ? 3.7 4.1 4.3 v hysteresis ? ? 0.1 0.2 0.4 v 4. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 5. for propagation delays, ?tpdh? refers to the specified signal going high; ?tpdl? refers to it going low. 6. guaranteed by design; not tested in production.
ADP3110A http://onsemi.com 5 applications information theory of operation the ADP3110A are single phase mosfet drivers designed for driving two n ? channel mosfets in a synchronous buck converter topology. the ADP3110A will operate from 5.0 v or 12 v, but have been optimized for high current multi ? phase buck regulators that convert 12 v rail directly to the core voltage required by complex logic chips. a single pwm input signal is all that is required to properly drive the high ? side and the low ? side mosfets. each driver is capable of driving a 3 nf load at frequencies up to 1 mhz. low ? side driver the low ? side driver is designed to drive a ground ? referenced low r ds(on) n ? channel mosfet. the voltage rail for the low ? side driver is internally connected to the v cc supply and pgnd. high ? side driver the high ? side driver is designed to drive a floating low r ds(on) n ? channel mosfet. the gate voltage for the high side driver is developed by a bootstrap circuit referenced to switch node (sw) pin. the bootstrap circuit is comprised of an external diode, and an external bootstrap capacitor. when the ADP3110A are starting up, the sw pin is at ground, so the bootstrap capacitor will charge up to v cc through the bootstrap diode see figure 4. when the pwm input goes high, the high ? side driver will begin to turn on the high ? side mosfet using the stored charge of the bootstrap capacitor. as the high ? side mosfet turns on, the sw pin will rise. when the high ? side mosfet is fully on, the switch node will be at 12 v, and the bst pin will be at 12 v plus the charge of the bootstrap capacitor (approaching 24 v). the bootstrap capacitor is recharged when the switch node goes low during the next cycle. safety timer and overlap protection circuit it is very important that mosfets in a synchronous buck regulator do not both conduct at the same time. excessive shoot ? through or cross conduction can damage the mosfets, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. the ADP3110A prevent cross conduction by monitoring the status of the external mosfets and applying the appropriate amount of ?dead ? time? or the time between the turn off of one mosfet and the turn on of the other mosfet. when the pwm input pin goes high, drvl will go low after a propagation delay (tpdldr vl). the time it takes for the low ? side mosfet to turn off (tfdrvl) is dependent on the total charge on the low ? side mosfet gate. the ADP3110A monitor the gate voltage of both mosfets and the switchnode voltage to determine the conduction status of the mosfets. once the low ? side mosfet is turned off an internal timer will delay (tpdhdrvh) the turn on of the high ? side mosfet likewise, when the pwm input pin goes low, drvh will go low after the propagation delay (tpddrvh). the time to turn off the high ? side mosfet (tfdrvh) is dependent on the total gate charge of the high ? side mosfet. a timer will be triggered once the high ? side mosfet has stopped conducting, to delay (tpdhdrvl) the turn on of the low ? side mosfet power supply decoupling the ADP3110A can source and sink relatively large currents to the gate pins of the external mosfets. in order to maintain a constant and stable supply voltage (v cc ) a low esr capacitor should be placed near the power and ground pins. a 1 f to 4.7 f multi layer ceramic capacitor (mlcc) is usually sufficient. input pins the pwm input and the output disable pins of the ADP3110A have internal protection for electro static discharge (esd), but in normal operation they present a relatively high input impedance. if the pwm controller does not have internal pulldown resistors, they should be added externally to ensure that the driver outputs do not go high before the controller has reached its under voltage lockout threshold. the ncp5381 controller does include a passive internal pull ? down resistor on the drive ? on output pin. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and the internal (or an external) diode. selection of these components can be done after the high ? side mosfet has been chosen. the bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. a minimum 50 v rating is recommended. the capacitance is determined using the following equation: c bst q gate v bst where q gate is the total gate charge of the high ? side mosfet, and v bst is the voltage droop allowed on the high ? side mosfet drive. for example, a ntd60n03 has a total gate charge of about 30 nc. for an allowed droop of 300 mv, the required bootstrap capacitance is 100 nf. a good quality ceramic capacitor should be used. the bootstrap diode must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on sw. the average forward current can be estimated by: i f(avg) q gate f max where f max is the maximum switching frequency of the controller. the peak surge current rating should be checked in ? circuit, since this is dependent on the source impedance of the 12 v supply and the esr of c bst.
ADP3110A http://onsemi.com 6 figure 2. output disable timing diagram 10% 90% drvh or drvl od t pdlod t pdhod v od _hi v od _lo figure 3. nonoverlap timing diagram 90% 10% 10% 90% 90% 10% 10% 90% 2v 2v drvl t pdldrvl t fdrvl t pdhdrvh t rdrvh t pdldrvh t fdrvh t rdrvl t pdhdrvl drvh ? sw sw in v pwm_hi v pwm_lo ADP3110A 4 3 2 5 6 7 8 1 vcc od in drvl pgnd sw drvh bst vout 12 v output enable 12 v pwm in figure 4. ADP3110A example circuit
ADP3110A http://onsemi.com 7 package dimensions ??? ??? ??? case 506bj ? 01 issue o *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldermask defined pin 1 reference a b c 0.10 2x 2x top view d e c 0.10 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e2 bottom view b 0.10 8x l 14 0.05 c ab c d2 e k 85 8x 8x (a3) c c 0.05 8x c 0.05 side view a1 a seating plane dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.64 1.84 e 3.00 bsc e2 1.35 1.55 e 0.50 bsc k 0.20 ??? l 0.30 0.50 note 3 l detail a optional construction l1 detail a 0.00 0.03 note 4 detail b 3.30 8x dimension: millimeters 0.63 1.55 1.85 0.50 pitch 8x 0.35 mounting footprint detail a
ADP3110A http://onsemi.com 8 package dimensions soic ? 8 d suffix case 751 ? 07 issue aj 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ADP3110A/d flexmode is a trademark of analog devices, inc. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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